1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device and a method of testing the same, and in particular to a dynamic semiconductor memory device allowing efficient detection of a failure that high data written into a memory cell erroneously changes into low data as well as a test method for the same.
2. Description of the Background Art
FIG. 22 is a circuit diagram specifically showing a memory cell of a dynamic semiconductor memory device in the prior art, and particularly a memory cell of a dynamic random access memory which will be referred to merely as a "DRAM" hereinafter. Referring to FIG. 22, a memory cell 25 is formed of a memory cell transistor 27 and a memory cell capacitor 29.
An operation of writing high data ("1" data) into memory cell 25 will be described below. In the following description, it is assumed that a power supply voltage is Vcc, and ground voltage is GND. Bit lines BL and /BL have been precharged to (1/2)Vcc level by an equalize/precharge circuit (not shown). A voltage higher than (Vcc+Vth) level is applied onto a word line WL, so that memory cell transistor 27 is turned on. Vth is a threshold voltage of memory cell transistor 27. After deactivation of the precharge/equalize circuit, a voltage at Vcc level is applied from an I/O line IO onto bit line BL. Meanwhile, a voltage at GND level is applied onto a bit line /BL from an I/O line /IO. Thereby, a storage node SN is set to a potential at Vcc level. Thus, high data is written into memory cell 25.
A failure which may occur in a DRAM will be described below. A manufacturing method and a structure of memory cells have been complicated to a higher extent in accordance with improvement of a manufacturing process technology of DRAMs. In accordance with this, there has been a growth in failures due to defects in processes and steps. The failures are, for example, a pause refresh failure and a disturb refresh failure. The pause refresh failure will now be described below. Due to N-P junction leak between a storage node SN and a substrate in a memory cell, high data already written in the memory cell erroneously changes into low data in some cases. This failure is the pause refresh failure. The disturb refresh failure is as follows. Due to a subthreshold leak current of memory cell transistor 27, charges accumulated in storage node SN flow out onto bit line BL, so that high data written in memory cell 25 erroneously changes into low data in some cases. This failure is called the disturb refresh failure. The error that the high data written in the memory cell changes into the low data will be referred to as an "HAL error" hereinafter.
Since an N-P junction leak current between storage node SN and the substrate in the memory cell 25 as well as a subthreshold leak current at memory cell transistor 27 are extremely small, it takes a considerably long time before the H.fwdarw.L error occurs after flow of charges from storage node SN set to the potential at Vcc level. In the conventional DRAM, therefore, detection of the H.fwdarw.L error requires a considerably long time, which disadvantageously increases a production cost.